The authors investigate a wafer scale tunnel junction fabrication method, where a plasmaetched via through a dielectric layer covering bottom Alelectrode defines the tunnel junction area. The ex situ tunnel barrier is formed by oxidation of the bottom electrode in the junction area. Room temperature resistance mapping over a 150 mm wafer gives local deviation values of the tunnel junction resistance that fall below 7.5% with an average of 1.3%. The deviation is further investigated by sub-1 K measurements of a device, which has one tunnel junction connected to four arrays consisting of N junctions (= 41, junction diameter 700 nm). The differential conductance is measured in single-junction and array Coulomb blockade thermometer operation modes. By fitting the experimental data to the theoretical models, the authors found an upper limit for the local tunnel junction resistance deviation of ~ 5% for the array of 2N +1junctions. This value is of the same order as the minimum detectable deviation defined by the accuracy of the authors’ experimental setup.